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Central Engineering – The Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro, and data centers. We address the bandwidth, capacity, and power issues faced by cloud computing and mega data centers that power the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many key areas, developing the most advanced chips and subsystem solutions to address the ever-increasing demand for higher data rates driven by video-on-demand, gaming, and other real-time data streams.

• Analyze block specifications and select appropriate topologies.
• Design analog blocks at the transistor level.
• Supervise layout activities, provide guidelines and conduct post-layout verifications.
• Model blocks and validate models.
• Collaborate with other teams to enhance existing solutions.
• Take responsibility for designing entire analog macros or IPs.
• Participate in cross-functional meetings and interact with other functions.
• Manage both pre-silicon and post-silicon tasks through to mass production.
• Train and mentor junior designers.

• Master’s degree and/or PhD in Electrical Engineering or related fields with 12-15 years of work experience.
• Proven experience in designing ICs from architecture definition to lab characterization and bringing them into volume production.
• Solid experience in analog design, preferably in the multi-GHz range; performing or supervising analog custom layout; using EDA CAD tools; measuring IC performance and debugging the design to correlate simulations to measurements.
• Direct project experience in at least one of the following areas a plus: Multi-Gbps electrical SerDes or electro-optical transceivers; advance CMOS nodes, including FinFET.
• Strong communication, presentation and documentation skills.

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